Integrated circuits (“ICs”) are incorporated into many electronic devices. IC packaging has evolved such that multiple ICs may be vertically joined together in so-called three-dimensional (“3D”) packages in order to save horizontal area on a printed circuit board (“PCB”). Another packaging method, referred to as 2.5D IC packaging, incorporates an interposer, which may be formed from a semiconductor material such as silicon, for coupling one or more dies to a PCB. However, memory and logic testing of 2.5D ICs can be costly and inefficient, involving a large area on the IC chip as well as external equipment to generate the testing signals. Additionally, such tests may only locate general problem areas rather than specific locations of errors.